Exploring channel doping designs for high-performance tunneling FETs

Abstract

Future high-performance low-power integrated circuits require compact logic devices with both steep subthreshold swing (SS) and large drive current (I ON ). Tunneling field-effect transistors (TFETs) can meet the first requirement but their I ON is severely limited either by the low source-channel tunneling probability or by the high source-to-drain tunneling leakage. One of the methods that can be employed to boost I ON is doping engineering. In particular (1) lowering the drain doping density elongates the drain depletion region and thus suppresses the leakage leading to improved SS (and ION). This scheme, however, is not scalable as a long drain length is needed to reach charge neutrality [1]; (2) embedding an opposite N+ doping layer next to the P+ source, i.e., the source-pocket (SP) design [2], or inserting a δ doping layer [3], can enhance the electric field at the source-channel tunnel junction and improve ION. It can be shown that the improvement increases as the pocket doping density (Np) increases, but in practice doping density has an upper limit. In this paper, we show that, (1) embedding a P+ drain pocket can also improve the SS (and ION) and it is more scalable than lowering the drain doping; (2) by resorting to P+ channel, we can further improve I ON of the SP design without having to increase N p .