Exploring back biasing opportunities in 28nm UTBB FD-SOI technology for subthreshold digital design

Abstract

Ultra-Thin Body and Box Fully Depleted silicon on insulator (UTBB FD-SOI) has been identified as attractive technology that respond to market trends in mobile applications. Digital subthreshold design techniques allow to operate at the minimum energy point, thus leading to considerable energy savings. In this work, the impact of back biasing is analyzed for the subthreshold region with different threshold voltage device options. We show that back biasing is an effective knob to achieve the minimum energy point when either high or low performance is demanded. By applying forward back bias voltage of 1.5 V to low threshold voltage transistors we achieved a frequency boost by 8.23x while maintaining the same consumed energy per cycle. Using regular threshold voltage transistors reversed back biased by 1.5 V, the leakage current was reduced 13.5x. Furthermore, we show that a single p-well approach should be used when no back biasing is needed in the subthreshold regime.