Exploration Methodology for 3D Memory Redundancy Architectures under Redundancy Constraints

Abstract

Redundancy repair is a commonly-used technique for memory yield improvement. In order to ensure high repair efficiency and final product yield, it is necessary to explore and develop the memory redundancy architecture carefully. However, due to the different failure distributions of memory arrays and various design constraints of memory architectures, it is difficult to explore the efficiency of the memory architecture thoroughly. In this paper, we propose a redundancy architecture exploration methodology to find the redundancy architecture with highest repair rate under redundancy constraints. Given a set of design constraints, failure distributions, and memory architectures, our methodology can explore at least 3(log2M* log2N* log2S) redundancy architectures systematically, where M, N, and S are the address sizes of memory row and column in a die, and the number of slices in the memory cube, respectively. In our experiments, the repair rates of 10 different 3D redundancy architectures with 3 different redundancy analysis algorithms in a given failure pattern distribution are simulated. The experimental result shows that the difference of the repair rates between the most efficient and least efficient memory redundancy architectures is up to 49.42%.