Exploiting the reconfigurability of the PAnDA architecture to overcome physical substrate variations

Abstract

Field programmable gate arrays (FPGAs) are widely used in applications where on-line reconfigurable signal processing is required. Speed and function density of FPGAs are increasing as transistor sizes shrink to the nano-scale. As these transistors reduce in size, intrinsic variability becomes more of a problem, as every physical instance of a design behaves differently, resulting in a decrease in fabrication yield. This paper describes an adaptive, evolvable architecture that allows for correction and optimisation of circuits directly in hardware using bio-inspired techniques. Similar to FPGAs, the programmable analogue and digital array (PAnDA) architecture introduced here can be reconfigured on a digital level for circuit design. Accessing additional configuration options of the underlying analogue level enables continuous adjustment of circuit characteristics at run-time, which enables dynamic optimisation of the mapped design's performance. Moreover, the yield of devices can be improved post-fabrication via reconfiguration at the analogue level, which can overcome faults caused by variability and process defects.