Exploiting STT-MRAM for approximate computing

Abstract

Spin Transfer Torque Magnetic RAM (STT-MRAM) is an emerging non-volatile memory technology and a potential candidate to replace SRAM in processor caches. However, STT-MRAM suffers from a high write latency and high write energy consumption which have to be addressed for energy-efficient on-chip caches. The non-volatility property of STT-MRAM can be relaxed by reducing the thermal stability factor to improve both the write latency and write energy of STT-MRAM. However, this leads to increase in retention failure and read disturb rates resulting in erroneous data stored in the cache. This problem can naturally be mitigated in the scope of approximate computing in which such errors can be tolerated at the application level. In this paper, we show how STT-MRAM technology can effectively be used for approximate computing by tuning technology and application parameters to achieve an acceptable level of correctness with significant gains. Results show that using our proposed approximate computing framework, the per-access write latency and energy can be improved up to 25% and 70%, respectively.