Exploiting Parallelization on Address Translation: Shared Page Walk Cache

Abstract

Current processors carry out a Page Table Walk to translate a virtual address into a physical address. This process requires several memory accesses to retrieve the entry from each of the levels of the Page Table Tree. As each main memory access has a large latency, the address translation process may penalize significantly the system performance. Translation Lookaside Buffers (TLBs) avoid completely these accesses by storing the most recent translations. But on a TLB miss a Page Table Walk is required. An effective way to accelerate it is introducing a cache inside/near the MMU to store partial translations.