Exploiting On-Chip Inductance in High Speed Clock Distribution Networks

Abstract

On-chip inductance effects can be used to improve the performance of high speed integrated circuits. Specifically, inductance can improve the signal slew rate (the rise time), virtually eliminate short-circuit power consumption, and reduce the area of the active devices and repeaters inserted to optimize the performance of long interconnects. These positive effects suggest the development of design strategies that benefit from on-chip inductance. An example of an industrial clock distribution network is presented to illustrate the process in which inductance can be used to improve the performance of high speed integrated circuits.