Exploiting large register sets

Abstract

The paper examines problems associated with the application of load-store RISC architectures with large register sets or compiler-driven register assignment to realtime system design methodologies involving many tasks and frequent context switches. Approaches to on-chip storage are reviewed and the threaded windows concept introduced as an efficient mechanism for managing register resources. Under this system the structure and use of registers may be dictated by the programmer, compiler and operating system according to the demands of procedure activation records, hardware-supported stacks, hardware-supported queues, and concurrent task contexts, as well as task and system global storage. The use and benefits of the system with sequential programs and in concurrent tasking environments are explored. The abilities and attributes of similar architectures are evaluated and planned developments of the threaded windows system are outlined.