Exploiting contention and congestion aware switch allocation in network-on-chips

Abstract

Network-on-chip system plays an important role to improve the performance of chip multiprocessor systems. As the complexity of the network increases, congestion problem has become the major performance bottleneck and seriously influence the performance of NoCs. Prior works have focused on designing effective routing algorithm based on collecting congestion and contention information to load balance the traffic. However, most prior works do not consider balancing the traffic load during switch allocation. Due to the lack of congestion information in switch allocation stage, switch allocator performs allocation only based on packet requests and thus aggravates the congestion in the ports of switch. In this paper, we propose to add the congestion and contention information into the switch allocation process and design an efficient on-chip switching strategy which utilizes the contention and congestion information to load balance the traffic and achieve efficient switch allocation. To further enhance the performance of our design, we carefully design our switch allocation strategy to balance the trade-off between traffic load balance and the matching efficiency in switch allocation. We evaluate our design under synthetic traffic and trace of parsec benchmarks. Our evaluations show this mechanism achieves optimal latency compared to best previous switch allocation strategies.