Experiments concerning the life testing of semiconductor devices—II. Life testing of transistors in switching operation mode

Abstract

Usual methods of d.c. electrical stress applied on transistors as a means of long-run life test and bound mainly to thermally activated surface degradation processes, are less informative in relation to degradation in switching service. Here, a method is described where transistors are tested in c.b. switching circuit with a fixed 50 Hz repetition rate and exactly adjustable amount of switching-on-and-off transient energies, allowing large batches to be tested economically. The executed life-testing apparatus, employing an all-solid-state 250 A pulser, is also dealt with. Accelerated test experiments showed that temperature plays only a minor role and the main parameters influencing degradation are the magnitude and duration of turn-over transients as well as the collector pulse current stress level. Degradation is related chiefly to volumetric causes, e.g. structural failures only when the pulse current level is sufficiently high. Experiments showed that collector current stress levels within the data-sheet limits were inefficient for developing the characteristic volumetric failure mechanisms, the latter being “masked” by usual surface degradation mechanisms. The suggested method is of most use as a screen-test.