Experiments and root cause analysis for active-precharge hammering fault in DDR3 SDRAM under 3 × nm technology

Abstract

This paper investigates the failure mechanism manifested in DDR3 SDRAMs under 3× nm technology. DRAM cells should retain the stored value if they are refreshed within the cell retention time of 64ms at minimum. However the charge in a DRAM cell leaked faster, and the values of the stressed cells could not be retained with valid yet stressful hammered accesses to a row. An experiment of accelerated discharging by hammered accesses was duplicated by a SPICE simulation with a TCAD device model of a DRAM cell. Experiments with commercial DDR3 discrete components from three major memory manufacturers were performed to confirm the validity of the SPICE simulation. The contributions of each in triggering and accelerating the failure mechanisms are investigated depending on the three test parameters—tRP, data pattern, and temperature—based on the experimental results. In the experiments, all commercial DDR3 components failed much earlier than the specified limit of allowed accesses. In the worst condition, the failure in a normal cell of a component occurred at 200K, which is 15.23% of the permitted cell retention time.