Experimental Verification of Scan-Architecture-Based Evaluation Technique of SET and SEU Soft-Error Rates at Each Flip-Flop in Logic VLSI Systems

Abstract

Irradiation test results demonstrate the validity of a scan FF technology for separately evaluating SET and SEU soft error rates (SERs) in logic VLSI systems. The SET and SEU soft errors mean the upset caused by latching an SET pulse that originates in combinational logic cell blocks and the upset caused by a direct ion hit to the FF, respectively. A test chip is fabricated using a 0.2-mum fully-depleted silicon-on-insulator standard cell library and irradiated under an LET of 40 MeV-cm2/mg. The SET and SEU soft error rates are successfully measured by the scan FFs on the test chip. A theoretical SET SER estimation from measured SET-pulse widths is also experimentally validated.