Experimental evaluation of high voltage hold-off capability of post-process mesa-isolated series standard CMOS transistors

Abstract

We report successful fabrication of high-voltage-holdable CMOS device which is MEMS post-processed from standard circuit fabricated on an SOI (Silicon on Insulator) wafer. The method physically isolates transistors by forming mesa-“islands” by isotropic Deep Reactive Ion Etching (DRIE), instead of classical P-N junction well isolation. The device is usable for high-voltage switching circuit for CMOS-deep-MEMS monolithic integrated device (fig. 1) which employs only standard CMOS and MEMS fabrication technologies. In this report, we evaluated high-voltage hold-off capability of fabricated series-connected MOSFET structures by experiments. Less than 1pA leakage current was measured on 40-series-connected mesa-isolated off-state standard 5V MOSFET on a LSI chip when 200 V was applied. And it was observed that voltage endurance was around 1000 V for 200-series-connected standard 5V MOSFET.