Experimental determination of the maximum post-process annealing temperature for standard CMOS wafers

Abstract

This paper reports on the experimental determination of the maximum post-process annealing temperature for standard 0.35 /spl mu/m CMOS wafers with aluminum based interconnections and tungsten plugs, without introducing significant modifications to their standard characteristics. The impact of increasing the post-processing temperature from 475/spl deg/C to 575/spl deg/C, for periods varying between 30 and 90 min, on both the front and back end is analyzed. 0.35 /spl mu/m CMOS technologies with different Al alloys, Al-1wt%Si-0.5wt%Cu (AlSiCu) or Al-0.5wt%Cu (AlCu), and different back end structures are considered. It is illustrated that the maximum annealing temperature is a function of the structure and composition of the interconnection layers and their maximum allowable resistance increase. It is also demonstrated that the transistor characteristics, the silicide quality and the leakage currents are as good as unaffected by annealing for 90 min at temperatures up to 525/spl deg/C.