Experimental determination of the impact of polysilicon LER on sub-100-nm transistor performance

Abstract

Photoresist line edge roughness (LER) has long been feared as a potential limitation to the application of various patterning technologies to actual devices. While this concern seems reasonable, experimental verification has proved elusive and thus LER specifications are typically without solid parametric rationale. We report here the transistor device performance impact of deliberate variations of polysilicon gate LER. LER magnitude was attenuated by more than a factor of 5 by altering the photoresist type and thickness, substrate reflectivity, masking approach, and etch process. The polysilicon gate LER for nominally 70 - 150 nm devices was quantified using digital image processing of SEM images, and compared to gate leakage and drive current for variable length and width transistors. With such comparisons, realistic LER specifications can be made for a given transistor. It was found that subtle cosmetic LER differences are often not discernable electrically, thus providing hope that LER will not limit transistor performance as the industry migrates to sub-100 nm patterning.