Abstract
Dislocation sidewall gettering (DSG) is an important method for the removal of device-compromising defects from optoelectronic devices such as detectors and light-emitting diodes. DSG involves patterned epitaxy or post-growth patterning and annealing, and allows misfit dislocations to elongate until they are captured by image forces at sidewalls. Despite this physical understanding of the process, practical application of DSG has often been guided by empirical trials due to the scarcity of modeling studies. In this work we apply a detailed model for lattice relaxation and dislocation dynamics to DSG in heteroepitaxial ZnSSe/GaAs (001), considering the effects of thickness, composition, growth temperature, and annealing, and we compare modeling and experimental results for this material system.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
