Experimental Analysis of Within-Die Process Variation in 65 and 180 nm Complementary Metal–Oxide–Semiconductor Technology Including Its Distance Dependences

Abstract

As the very large scale integration (VLSI) circuits move deeper into the range of sub-100 µm processes due to the continued scaling efforts, designers increasingly face the variations of design parameters as major roadblocks. These variations include the deviation of process, voltage, and temperature values from the nominal specifications and are of paramount concern as they result in a deviation of the performance of ICs from the originally intended design. Thus, variations reduce the yield of the chip production and increase design cost and the design timing schedule. In this paper, we are presenting location-based within-die variation trends in 65 nm technology across the die, which are derived from measured delays of adjustable ring oscillators. The measured data of the test chips in a 65 nm complementary metal–oxide–semiconductor (CMOS) technology indicate that the magnitude of the position based relative variation is 3–7 times larger than for 180 nm technology. At low voltage (0.7 V), this relative variation is significantly increased (>3 times) in comparison to the variation at nominal supply voltage.