Abstract

In order to solve the problem of road congestion, a smart traffic management system is designed in this paper. The hardware control language Verilog for FPGA is used to implement logic control. The RS232 serial port and UART communication protocol are used to realize data communication and status visualization. YOLOv3 is used in conjunction with OpenCV for data collection. Combined with the shortest path optimization algorithm, an intelligent transportation scheme is given. Analog circuits are built using Proteus software for simulation verification. And the laboratory experiment box is used for physical verification.

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