Experiment design, defect analysis, and results for the wave soldering of small outline integrated circuits

Abstract

Experiments were conducted to determine an optimum footprint design for small-outline integrated-circuit (SOIC) surface mount packages that will be wave soldered to the back sides of PC boards. SO-8 SOIC surface mount pad dimensions, relative component positions, and solder mask openings were evaluated to determine a footprint configuration that would reduce solder bridges and solder skips (defects typical of the wave soldering operation), thereby providing acceptable assembly yields. The two experiments were of a screening nature and were conducted in order to compare three alternative pad lengths, two end pad widths, two internal pad widths, and two solder mask openings. The two experiments were differentiated by the nominal spacing, in both the X and Y directions, between SOICs. The results of both experiments provide evidence that SO-8 SOICs can be wave soldered successfully and that, when solder bridges or skips occur, the defect rate is below the acceptance level. The most robust design based on a defect analysis of 276480 solder joints and knowledge of the placement tolerance windows is the one with a pad length of 60 mil, an end pad width of 80 mil, and an inner pad width of 20 mil. The design was used on 576 solder joints and no defects were found. The best solder mask configuration was the individual opening around each solder pad. >