Abstract
Logic and Digital Design is an introductory level course for electrical engineering students at the Department of Electrical Engineering, University of Wisconsin-Platteville. This paper describes the development of using design automation tools in the course. Since Fall 1993, a realistic design environment has been created. Through laboratory work and a comprehensive final project, not only students have learned fundamental knowledge of the logic and digital design, but also they have used the extensive facilities in the laboratory to undertake the design and integration of state machine. In the course, several tools have been introduced gradually, which include schematic capture tools (OrCAD, MAX+PLUS II), simulation tool (SYNOPSYS, MAX+PLUS II) hardware design language and synthesis (AHDL, Programmer). At the end of the course, each student is required to design, test and implement and demonstrate his/her own state machine using CPLD devices (ALTERA). This paper also describes the accomplishments of the student projects during the academic year of 1996.
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