Experience in fabricating semiconductor devices using ion implantation techniques

Abstract

The described process of ion “implantation” is defined as one in which the distribution of the arrested ions is determined by the target material and the species, energy, integrated flux and relative orientation of the incident ions. Energies utilized in this technique are sufficiently high (greater than 50 keV) to minimize sputtering and to produce useful junction depths without invoking the process of “channeling” along preferred crystal planes. The resulting process is highly controlled and can be used to fabricate semiconductor devices by implanting through a passivating surface oxide. Spectroscopically pure 11B and 31P ion beams are routinely accelerated to energies between 50 keV and 400 keV to produce p- and n-type layers in silicon, respectively. The following p-n junction devices have been successfully fabricated during the past 4 1 2 year: 1. a. Solar cells: consistent state-of-the-art cells with efficiencies greater than 13% under tungsten (2800° K) illumination and 10% under solar (air mass zero) illumination. 2. b. Radiation detectors: passivated single counters (1.27 cm dia.) and spectrometer arrays with depletion depths of 1 mm (breakdown voltages > 700 V), dead layers less than 0.2 μm and best room temperature resolution of 60 keV. 3. c. Unipolar field effect transistors: transconductance greater than 2000 μmho. 4. d. Bipolar transistors: β > 40. Preliminary results on extension of the technique to wide band-gap materials are discussed.