Abstract
Multicore architecture is applied to contemporary avionics systems to deal with complex tasks. However, multicore architectures can cause interference by contention because the cores share hardware resources. This interference reduces the predictable execution time of safety-critical systems, such as avionics systems. To reduce this interference, methods of separating hardware resources or limiting capacity by core have been proposed. Existing studies have modified kernels to control hardware resources. Additionally, an execution model has been proposed that can reduce interference by adjusting the execution order of tasks without software modification. Avionics systems require several rigorous software verification procedures. Therefore, modifying existing software can be costly and time-consuming. In this work, we propose a method to apply execution models proposed in existing studies without modifying commercial real-time operating systems. We implemented the time-division multiple access (TDMA) and acquisition execution restitution (AER) execution models with pseudo-partition and message queuing on VxWorks 653. Moreover, we propose a multi-TDMA model considering the characteristics of the target hardware. For the interference analysis, we measured the L1 and L2 cache misses and the number of main memory requests. We demonstrated that the interference caused by memory sharing was reduced by at least 60% in the execution model. In particular, multi-TDMA doubled utilization compared to TDMA and also reduced the execution time by 20% compared to the AER model.
Highlights
Owing to the increased use of sensors in avionics systems, the number of tasks to be executed increased, and this requires more computing power
We demonstrate that multi-time-division multiple access (TDMA) can reduce interference due to memory sharing by 60%
We show that multi-TDMA reduces the execution time by 1% and 23% respectively compared to TDMA and acquisition execution restitution (AER)
Summary
Owing to the increased use of sensors in avionics systems, the number of tasks to be executed increased, and this requires more computing power. Multicore architectures have been introduced in avionics systems [1]. This allows for the execution of complex tasks, but unexpected problems may occur because multiple cores share hardware resources. These LRUs consist of a federated architecture, connected via buses, such as, the RS-232, and 1553 analog buses. To deal with more features in aircraft, the IMA architecture [17,18] has been proposed
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