Abstract

Summary form only given. The International Technology Roadmap of Semiconductors (ITRS) plans to introduce in production 50 nm node CMOS devices by 2011. These devices will require source and drain extensions depths in the 10 nm range. In order to control devices manufacturability, shallow extensions of 11 to 19 nm and 20 to 40 nm deep contact heavily doped source and drains will be needed. An alternative approach to suppression of Transient Enhanced Diffusion (TED) and enhancement of activation, which is necessary for shallow junctions in the range of 10 nm, is LTP (Laser Thermal Processing) or even GILD (Gas Immersion Laser Doping). This approach offers the possibility to suppress (TED) by applying ramp up and down times in the order of hundreds of nanoseconds which enables shallow junction depth, very abrupt profiles and a solubility limit higher than that usually encountered with conventional rapid thermal process. The main benefits of the laser processing are: low thermal budget very low or no diffusion under the gate, low contact resistivity and high junction abruptness.

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