Examining the Performance Impact of NoC Parameters for Scalable and Adaptive FPGA-Based Network-on-Chips

Abstract

In this paper we propose a methodology for investigating the impact of basic Network-on-Chip (NoC) parameters and self-adaptive scheme in the context of the Field Programmable Gate Array (FPGA). With our proposed methodology that is based on the Bayesian networking model we examined the effects of flit buffer depth, flit data width and virtual channel parameters through an extensive experimentation and simulation for scalable and adaptive NoC on Xilinx Virtex7 FPGA device. To demonstrate the flexibility and extensible design space coverage of our methodology, we design and present hardware synthesis results of 96 different NoCs configurations. We used a cycle accurate simulation system and drive the NoCs with four different traffic patterns and varying number of virtual channels (VCs) and show the resulting load-delay curves. Our results show that, for scalable and adaptive NoC, the flit data width and flit buffer depth parameters have the largest impact on FPGA area and clock frequency. We show that these parameters need to be properly adjusted for better run-time performance of the FPGA. Moreover, the neighbor traffic pattern with 4 VCs offer the best performance with 95% throughput, low latency and efficient silicon area in both Mesh and Torus networks.