Abstract
Full three-dimensional process and device simulations of short channel MOS transistors with gate edge roughness were performed. The amplitude and spatial wavelength of the edge roughness was varied systematically. Effects of correlated/anti-correlated right/left edge roughness were also investigated. Simulation results indicate that low spatial frequency anti- correlated edge roughness causes the worst degradation in device performance whereas low frequency correlated edge roughness causes the least device degradation. High spatial frequency edge roughness causes moderate device degradation, and the effect is independent of whether the gate edge roughness is correlated.
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