Examination of mechanical stresses in silicon substrates due to lead–tin solder bumps via micro-Raman spectroscopy and finite element modelling

Abstract

Due to the fact that semiconductor devices have decreased significantly in geometry and increased enormously in electronic design complication, flip-chip packaging technology was launched to increase input/output count, improve electrical performance, reduce packaging size and be cost effective. The Intel®Pentium®III microprocessor uses the popular ball grid array (BGA) packaging technique. BGA is one of the most common flip-chip packaging techniques used for microprocessor applications. However, mechanical stresses induced by the flip-chip process are major concerns for the reliability of such devices.Micro-Raman spectroscopy (μRS) is a powerful technique for investigating the spatial extent of strain fields in microelectronic devices. In this study, the strain fields imposed on the underlying silicon substrate due to the lead–tin solder bump process in BGA packaging have been investigated in pre- and post-reflowed samples using μRS and finite element modelling (FEM). For pre-reflowed samples, an approximate uniaxial compressive stress of 200 MPa is developed near the edge of the under bump metallization (UBM). However, a tensile stress up to ∼300 MPa is found for post-reflowed samples.Two-dimensional (2D) plane strain FEM has also been performed. The magnitudes and spatial distribution of the stresses after the reflow process are in good agreement with the micro-Raman results.