Abstract

The primary focus of this paper is the development of a hierarchical symbolic analysis method, which can be used to generate symbolic performance models (SPMs) for large parasitic-inclusive analog circuits. In this paper, a new exact hierarchical technique is proposed, where transfer functions (TF) are synthesized for a general interconnection template (GIT) of two subcircuits. Extremely efficient element-coefficient diagrams (ECD) are used for symbolic analysis of subcircuits. The results of TF-synthesis of a GIT, lead to the development of an easily automatable symbolic analysis method. The efficiency and scope of this method is then demonstrated on few common large analog networks.

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