Abstract
The aim of design space exploration (DSE) is to identify implementations with optimal quality characteristics which simultaneously satisfy all imposed design constraints. Hence, besides searching for new solutions, a quality evaluation has to be performed for each design point. This process is typically very expensive and takes a majority of the exploration time. As nearly all the explored design points are sub-optimal, most of them get discarded after evaluation. However, evaluating a solution takes virtually the same amount of time for both good and bad ones. That way, a huge amount of computing power is literally wasted. In this paper, we propose a solution to the aforementioned problem by integrating efficient approximations in the background of a DSE engine in order to allow an initial evaluation of each solution. Only if the approximated quality indicates a promising candidate, the time-consuming exact evaluation is executed. The novelty of our approach is that (1) although the evaluation process is accelerated by using approximations, we do not forfeit the quality of the acquired solutions and (2) the integration in a background theory allows sophisticated reasoning techniques to prune the search space with the help of the approximation results. We have conducted an experimental evaluation of our approach by investigating the dependency of the accuracy of used approximations on the performance gain. Based on 120 electronic system level problem instances, we show that our approach is able to increase the overall exploration coverage by up to six times compared to a conservative DSE whenever accurate approximation functions are available.
Highlights
The design of embedded systems is continuously becoming more arduous as complex applications have to be mapped onto heterogeneous hardware platforms
We can be sure that performance and quality differences stem from our contribution and not from a methodological mismatch
While we focus this work on networks-on-chip (NoCs) rather than bus based architectures, our approximation based design space exploration (DSE) is not limited to network on chip (NoC) but can be adopted for other architectures as well
Summary
The design of embedded systems is continuously becoming more arduous as complex applications have to be mapped onto heterogeneous hardware platforms. Besides good performance of the resulting system implementation, further objectives like energy requirements, monetary costs, and reliability are typically conflicting with each other so that a single optimal solution, which dominates (i.e., evaluates better for all objective) all other design points, does not exist. A set of Pareto optimal, mutually non-dominated design points (Pareto front) is obtained that render the best compromise solutions to a given problem. In order to obtain the Pareto front, a design space exploration (DSE) including a multi-objective optimization is executed which can be conceptually split into a search for feasible solutions, an evaluation, and an optimization of found solutions. The search is performed in parameter space by filtering infeasible solutions from the set X of all solutions. After the Pareto filter, only Pareto optimal design points remain in the set XP
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