Evolution of nanocrystalline silicon thin film transistor channel layers

Abstract

Thin film transistors (TFTs) of nanocrystalline silicon (nc-Si:H) can be made at temperatures as low as 150 °C and are capable of p and n channel operation. High carrier mobility and low off current can be achieved in the staggered top-gate, bottom-source/drain geometry. Beginning the growth of nc-Si:H with a seed layer placed underneath the TFT promotes the structural evolution of the nc-Si:H channel layer and raises the carrier field effect mobilities and current ON/OFF ratio. We study the correlation between the evolution of the nc-Si:H structure and TFT electrical characteristics and determine the onset thickness of the continuously crystalline channel. The nc-Si:H surface topography is characterized by atomic force microscopy (AFM) and scanning electron microscopy (SEM), while electrical properties are examined by TFT performance. 50-nm thick channel layers have the smallest surface roughness and yield transistors with the highest hole and electron field effect mobilities of ∼0.25 and ∼40 cm 2 V −1 s −1, respectively.