Evolution of monolithic phase-locked loops

Abstract

The phase-locked loop (PLL) is a key building block in both wireline and wireless systems. In the wireline system, low-jitter clock generation and clock-and-data recovery (CDR) circuits are critical in high data rate I/O links. In the wireless system, the delta-sigma (DS) fractional-N frequency synthesizer plays an important role in modern transceivers not only as a local oscillator but also as a phase modulator with direct-digital modulation. Due to various applications, diversified PLL architectures and circuit techniques have been proposed in consideration of performance, power, and cost, making it difficult for circuit designers to choose the right design solution. Hence, it would be somewhat helpful for circuit designers to gain a historical view of the PLL integrated circuit. This chapter reviews major innovations in the development of early-stage complementary-metal-oxidesemiconductor (CMOS) PLLs. In the first section, a brief overview of the development of PLL integrated circuits (ICs) is introduced. Then, major innovations in the history of CMOS PLLs are described in the following sections by considering architecture, circuit, and application aspects.