Evolution of intrachip interconnects and performance constraints

Abstract

This work aims at defining the marks that optoelectronic solutions will have to beat for replacing electric interconnects at chip level. Thus, we first anlayze the communication performance of future electrical interconnects considering the reduction of the lithographic feature size λ from 0.7 to 0.05 μm. We mostly analyze the results with reduced units: Lengths are calculated in multiples of λ times are compared to the chip clock cycle Tc that we estimate from the foreseeable evolution of the processor operation frequency. From our simulations, we conclude that: 1) it does not seem necessary to consider the integration of optical interconnects (OI) over distance shorter than 1000λ, because the performacne of electric interconnects is sufficient; 2) The penetration of IOs between blocks separated by more than 10λ could be envisaged provided that the present performence of OIs could be dramatically improved to beat electric solutions at chip level. New generations of low-threshold high-effieincy VCSELs and ultra-fast high-efficiency photodiode are needed; 3) The first possible application of OIs in chips is likely not for inter-block communication but for clock distribution as the energy constaints are weaker and because the clock tree is an extremely long interconnect.