Evolution of Chip-Scale Heterodyne Optical Phase-Locked Loops Toward Watt Level Power Consumption

Abstract

We design and experimentally demonstrate two chip-scale and agile heterodyne optical phase-locked loops (OPLLs) based on two types of InP-based photonic-integrated coherent receiver circuits. The system performance of the first-generation OPLL was improved in terms of offset-locking range, and power consumption with the use of a power efficient and compact photonic-integrated circuit (PIC). The second-generation PIC consists of a 60-nm widely tunable Y-branch laser as a local oscillator with a 2 × 2 multimode interference (MMI) coupler and a pair of balanced photodetectors. This PIC consumes only 184-mW power in full operation, which is a factor of 3 less compared to the first-generation PIC. In addition, the sensitivity of these OPLLs was experimentally measured to be as low as 20 μw. A possible solution to increase the sensitivity of these OPLLs is also suggested.