Even-Harmonic Class-E CMOS Oscillator

Abstract

This article proposes the theory and implementation of an even-harmonic class-<inline-formula> <tex-math notation="LaTeX">$E$ </tex-math></inline-formula> CMOS oscillator that displays an excellent phase noise performance. Starting from zero voltage switching (ZVS) and zero derivative switching (ZDS) conditions, expressions for drain voltage and current waveforms are derived. Based on a 1:1 transformer, a custom-designed tank is proposed, which satisfies ZVS and ZDS conditions for the core transistors, provides high-<inline-formula> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> resonances at both fundamental and second harmonics of the oscillation frequency, and yields a passive voltage gain from the drain to the gate of the core transistors. Satisfying ZVS and ZDS conditions reduces the overlap between the voltage and current waveforms of the transistor that increases the power efficiency of the oscillator. Furthermore, it widens the flat span of the semi half-sinusoidal voltage waveform, where the impulse sensitivity function (ISF) is negligible. Therefore, the conversion of the core transistor noise to phase noise is reduced. These features improve the oscillator&#x2019;s figure of merit (FoM) in comparison with state-of-the-art CMOS oscillators. The prototype of the even-harmonic class-<inline-formula> <tex-math notation="LaTeX">$E$ </tex-math></inline-formula> oscillator is implemented in a 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology. At 4 GHz, it exhibits a phase noise of &#x2212;152.75 dBc/Hz at a 10-MHz offset while providing a 10.6% tuning range. The corresponding FoM is 197.9 dBc/Hz. The circuit draws 7 mA from a 0.7-V supply, and the die area is 0.23 mm².