Evalulation of Electrodeposited Photoresists for use in the Fabrication of an Optochip Silicon Interposer

Abstract

As 3D packaging technology and designs evolve, increasing complexity has been introduced in the fabrication of these devices. The integration of optical devices along with electronic wired elements such as the package platform identified in image sensors is one prime example where the design elements of the structures significantly increase the topography on the surface of the system. This multiplies the degree of difficulty in the lithography solution chosen to facilitate fabrication of these structures. The use of electrodeposited (ED) photoresists is a technology platform that has been used in MEMs, printed circuit boards, backside vias, etc, and can play a significant role in enabling new 3D packaging solutions. In this research, the successful fabrication of an Optochip silicon interposer, which integrates electrical and optical components onto a single substrate with high density interconnection, was enabled through use of electrodeposited (ED) photoresist. The Optochip interposer was manufactured in a standard 200 mm semiconductor fab and this precipitated the process integration requirement of first etching “optical vias” into the silicon at wafer-level prior to the final lithography steps. As such, challenging topography was introduced into the system. A resist solution able to address the following conditions was required: 1) sufficient conformal coating into large optical vias measuring 150 um diameter by 200 um depth, 2) no resist pull-back over sharp 90 degree angle corners where the optical vias met the wafer surface, 3) ability to resolve 30 um diameter surface pads at 50 um pitch and 4) chemical resistance to Ni and cyanide-based Au plating baths. This presentation will discuss how various photoresists were examined that resulted in ED photoresist being chosen for the aforementioned application. Both negative-tone and positive-tone ED photoresists were considered. Experiments to study process parameters and environmental factors on product yield were performed using test wafers with optical vias. These experiments resulted in positive-tone ED photoresist being selected. Test wafers plated with NiAu resulted in ~ 90% process yield. The presentation will conclude by demonstrating the ability to achieve good yield on integrated product wafers.