Evaluation of TiO<inf>2</inf>/SiO<inf>2</inf> dielectric thin films to overcome the challenges of CMOS scaling

Abstract

The Semiconductor Industry Association (SIA) expectations are to achieve the 22nm technology at the end of 2018. So aggressively continuation in physical size scaling of Complementary Metal Oxide Semiconductor Transistor (MOSFET) experiences difficulties due to various factors. The conventional oxide can be scaled down to two atomic layers of about 7 A˚ because of limitations of leakage current, interface trap densities, and limitations of statistical parameters of fabrications. This paper addresses the main challenges and analyzes of the critical issues of MOS gate dielectric in nanometer range and provides an alternate material. So MOS capacitors were fabricated with and TiO 2 / SiO 2 as dielectric material on P-type silicon wafers and characterized for microelectronics application. TiO 2 films were characterized using XRD, Capacitance-voltage (C-V) and Current-voltage (I-V) measurements. The measured results show that TiO 2 /SiO 2 dielectric layer has desirable properties compared to TiO 2 films grown by DC magnetron sputtering.