Evaluation of the impact of defects on threshold voltage drift employing SiO2 pMOS transistors

Abstract

One of the main drawbacks of the continuous scaling of MOS transistors is the increase in variability of the device characteristics, e.g. threshold voltage, SS, mobility, which represents a formidable challenge for robust electronic circuits. Device variability issues are categorized into contributions from time-zero threshold voltage variations, as well time-dependent effects, i.e. variability in the drift of the threshold voltage. The time-dependent effect is a consequence of charge trapping at electrically active defects located inside the insulator or at the insulator/semiconductor interface as well as the creation of new defects. Furthermore, the defects appear statistically distributed in terms of their number and trap location which can lead to immediate failure of devices and circuits for unfortunate combinations (killer defects) which becomes increasing critical for nanoscale nodes. In this work, we thoroughly investigate the distribution of the contribution of the defects on the device behavior. Our results provide a simple mathematical expression to link device geometry and variability. Furthermore, by combining single-defect analysis with a defect-centric model our approach enables us to accurately extract valuable information about the time-dependent variability for a whole technology. While existing approaches focus on either large-area or nanoscale nodes, our model holds for both regimes and is of high relevance for the optimization of circuits towards high immunity against charge trapping.