Evaluation of Seebeck coefficients in n- and p-type silicon nanowires fabricated by complementary metal–oxide–semiconductor technology

Abstract

Silicon-based thermoelectric nanowires were fabricated by using complementary metal–oxide–semiconductor (CMOS) technology. 50 nm width n- and p-type silicon nanowires (SiNWs) were manufactured using a conventional photolithography method on 8 inch silicon wafer. For the evaluation of the Seebeck coefficients of the silicon nanowires, heater and temperature sensor embedded test patterns were fabricated. Moreover, for the elimination of electrical and thermal contact resistance issues, the SiNWs, heater and temperature sensors were fabricated monolithically using a CMOS process. For validation of the temperature measurement by an electrical method, scanning thermal microscopy analysis was carried out. The highest Seebeck coefficients were − 169.97 μV K−1 and 152.82 μV K−1 and the highest power factors were 2.77 mW m−1 K−2 and 0.65 mW m−1 K−2 for n- and p-type SiNWs, respectively, in the temperature range from 200 to 300 K. The larger power factor value for n-type SiNW was due to the higher electrical conductivity. The total Seebeck coefficient and total power factor for the n- and p-leg unit device were 157.66 μV K−1 and 9.30 mW m−1 K−2 at 300 K, respectively.