Evaluation of performance of parallel processors in a real-time environment

Abstract

The use of parallelism to achieve greater processing thruput for computational problems exceeding the capability of present day large scale sequential pipelined data processing systems has been proposed and in some instances hardware employing these concepts has been built. Several approaches to hardware parallelism have been taken including multiprocessors which share common storage and input-output facilities but carry out calculations with separate instruction and data streams; array processors used to augment a host sequential type machine which executes a common instruction stream on many processors; and associative processors which again require a host machine and vary from bit to word oriented processors which alternatively select and compute results for many data streams under control of correlation and arithmetic instruction streams. In addition, the concept of pipelining is used both in arithmetic processors and entire systems, i.e., vector machines to achieve parallelism by overlap of instruction interpretation and arithmetic processing.