Evaluation of mirror full adder circuit reliability performance due to negative bias temperature instability (NBTI) effects based on different defect mechanisms

Abstract

Negative bias temperature instability (NBTI) is an aging effect that can cause the threshold voltage to be shifted hence reduce the drain current. This will subsequently leads to main aging effect in sub-micron CMOS circuits. The NBTI defect mechanisms consist of interface trap generation and hole trapping effect. The main objective of this work was to study the impact of NBTI effect on the circuit performance based on different defect mechanisms. The percentage of how the performance affected in terms of delay by different defect mechanisms will be evaluated based on mirror full adder circuit. To study the reliability issues on circuit, model cards based on 45nm, 65nm and 90nm Predictive Technology Model (PTM) have been used along with the MOSRA model. The impact of NBTI on this circuit were evaluated based on the performance of the circuit which is the propagation delay. To understand the effect of different defect mechanism, analysis at the device level was conducted where the threshold voltage shift of the p-MOSFETs were evaluated. It is shown that the delay degradation will increase with the increasing of the temperature.