Evaluation of mechanical stresses in silicon substrates due to lead–tin solder bumps via synchrotron X-ray topography and finite element modeling

Abstract

Solder-based flip-chip packaging has prompted interest in integrated circuit (IC) packaging applications due to its many advantages in terms of cost, package size, electrical performance, input/output density, etc. The ball grid array (BGA) is one of the most common flip-chip packaging techniques used for microprocessor applications. However, mechanical stresses induced by the flip-chip process can impact adversely on the reliability of products. Synchrotron X-ray topography (SXRT), a non-destructive technique, has been employed to investigate the spatial extent of strain fields imposed on the underlying silicon substrate for Intel ®Pentium ®III microprocessors due to the lead–tin solder bump process for BGA packaging. Large area and section back-reflection SXRT images were taken before and after a simulation of the reflow process at 350 °C in atmosphere. The presence of induced strain fields in the Si substrate due to the overlying bump structures has been observed via the extinction contrast effect in these X-ray topographs. In addition, orientational contrast effects have also been found after the reflow process due to the severe stresses in the underlying silicon beneath the lead bumps. The estimated magnitudes of stress, ∣ σ∣, imposed on the underlying silicon were calculated to be of the order of 100 MPa. The spatial strains in the underlying silicon were relieved dramatically after the lead bumps were removed from the wafer, which confirms that the bumps are indeed a major source of strain in the underlying Si. Finite element modeling (FEM) has also been performed in two-dimensional (2-D) plane strain mode. The magnitudes and spatial distribution of the stresses after the reflow process are in good agreement with the SXRT results.