Evaluation of Information Leakage of Cryptographic Chip Based on Variance

Abstract

The cryptographic chip in system must be evaluated for side channel leakage detection before coming into service. However, the existing evaluation technology is too inefficient. This letter decomposes the variance of the traces of power consumption into variance of the sensitive variable and noise to estimate the signal-to-noise (SNR). According to the relationship between the success rate (SR) of the power analysis attack, SNR and conditional mutual information, the minimum number of traces is computable to evaluate the information leakage of the cryptographic chip. This method effectively estimates the minimum number of power traces when the SNR of power consumption is greater than 0.1. When the SNR is less than 0.1, the result calculated by this method is consistent with the change trend of the simulation, which means that the result also evaluates the ability of cryptographic chip to resist power analysis attacks. The method improves the evaluation efficiency by at least 60000 times compared with the simulation of CPA.