Abstract

The complexity of circuits to implement on FPGA has necessitated to explore hierarchical interconnect architectures. A large body of work shows that a good partitioning hierarchy, as measured by the associated Rent parameter, will correspond to an area-efficient layout. We define the architecture Rent parameter of a netlist to be the lowest bound on the Rent parameter of any partitioning hierarchy of the netlist. Experimental results show that a combination between a multilevel bottom-up clustering and a top-down refinement generates partitioning hierarchies whose Rent parameters are lower than those of other methods.

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