Abstract
The article deals with the choice of the architecture of digital signal processing units for implementing the PSK signal detection scheme. As an assessment of the effectiveness of architectures, the required number of shift registers and computational processes are used when implementing the "system on a chip" on the chip. A statistical estimation of the normalized code sequence offset in the signal synchronization scheme for various hardware block architectures is used.
Highlights
The hardware architecture of the digital signal processing units is one of the priority areas in improving the consumer qualities of digital transmitting devices and reducing their cost
Reception of the band signal begins with the synchronization of the code sequence of the receiver
The detection of the signal is carried out by means of consistent filtering according to the known code sequence
Summary
Evaluation of hardware costs of implementing PSK signal detection circuit based on "system on chip". To cite this article: A V Sokolovskiy et al 2018 J. View the article online for updates and enhancements. - A MEMS hardness sensor with reduced contact force dependence based on the reference plane concept aimed for medical applications Yusaku Maeda, Kyohei Terao, Fusao Shimokawa et al. - The energy-efficient implementation of an adaptive-filtering-based QRS complex detection method for wearable devices Shudong Tian, Jun Han, Jianwei Yang et al. This content was downloaded from IP address 79.110.19.161 on 30/08/2018 at 02:44
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