Evaluation of fabrication process and barrier structure for interface-modified ramp-edge junctions

Abstract

For SFQ circuits using high- T c Josephson junctions, it is very important to reduce the I c spread of the junctions. We have studied several causes of the I c spread in interface-modified ramp-edge junctions. First, the relation between the structure and the fabrication process of the barrier has been examined. Reflection high energy electron diffraction pattern observation in the recrystallization process of the interface-modified barrier and transmission electron microscopy observation indicate that several types of barrier structures appear by changing the electron cyclotron resonance ion-bombardment and subsequent annealing conditions. Ion bombardment at a high acceleration voltage of 700 V induces no cubic layer at the interface, while several types of cubic structure can be observed for lower acceleration voltages (300–500 V). Thus, distribution of ion beam energy is one of the important factors determining the I c spread. We also report the importance of other factors including the uniformity of ion beam for making an amorphous layer, and the base-electrode film quality such as the density of outgrowth or particles and the roughness of the ramp surface. By improving these factors in the junction fabrication process, an I c spread of 17% has been obtained for an array of 1000JJs with a relatively small average I c of 0.1 mA, suggesting a possibility of further improvement for junctions with a higher J c.