Evaluation of bank-based multiport memory architecture with blocking network

Abstract

The bank-based multiport memory is a better composition approach to realizing realistic chip area and high access bandwidth than a conventional N-port memory cell approach. However, this method is unsuitable for large numbers of ports and banks because the hardware resources of the crossbar network which connects the ports and banks increase in proportion to the product of the numbers of ports and banks. In order to solve this problem, this paper proposes a new bank-based multiport memory architecture using a blocking network instead of a crossbar network. Many blocking networks have been researched so far. However, these researches evaluated hardware resources based on the number of switches, but the compositions and circuit scale of the switches used in crossbar network and blocking network are different. Hence, this paper compares the number of transistors to show that the bank-based multiport memory using the blocking network achieves high access bandwidth with smaller hardware resources than the conventional approach. According to our results, our approach achieves the same access bandwidth with half the number of transistors, for 512 ports and 512 banks. © 2006 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 89(6): 22–33, 2006; Published online in Wiley InterScience (www. interscience.wiley.com). DOI 10.1002/ecjc.20205