Evaluation of adaptive processes for the embedding of bare dies in IC substrates

Abstract

Highly integrated, advanced multi-chip packaging solutions combine application, logic and computing dies with memory or components for power management in a single package. A solution to achieve low fabrication costs is the close embedding of thin dies in IC Substrates based on large formats $(600\times 600 mm^{2})$, known from PCB fabrication. In a consortium of partners from industry and research advanced technologies for Panel Level Packaging (PLP) are developed. Here, dies are symmetrically embedded under low stress into pre-manufactured IC substrates. The Embedding in Cores with Cavities (EiCC) targets towards low cost and thin packages $(\lt 150 \mu m)$ with multiple, heterogeneous components. The biggest disadvantage is the potentially low yield due to low assembly accuracy and process tolerances during the embedding process. This paper presents recent results to optimize the yield of the EiCC process chain. We assemble two $6\times 6mm^{2}, 100\mu m$ thin dies with 25 $\mu m$ high Cu pillars face down on a temporary adhesive foil with two assembly concepts, varying assembly throughput and accuracy. After embedding the stack in Ajinomoto Build-Up Film (ABF), laser drilled vias and a semi-additive Process (SAP) with 10 $\mu m$ lines and space with a copper thickness of 5 $\mu m$ acts as electrical routing between the daisy chain structured dies. Based on practical work we compare the known status of precision focussed manufacturing against a rule-based system that acquires data with a Coordinate Measurement Machine (CMM), rearranges fabrication plans and forwards data along the process chain.