Abstract
Design space exploration is used to shorten the design time of System-on-Chips (SoCs). The models used in the exploration need to be both accurate and fast to simulate. This paper introduces a multi-level communication cost to improve the accuracy of the abstracted system models. During the simulation, one of three different communication costs is applied for each inter-task communication event based on the mapping of the communicating tasks. The accuracy of three system abstraction models including the presented communication cost is evaluated using a Motion-JPEG (M-JPEG) application described in Unified Modeling Language (UML). According to the results, the average error in frames per second (FPS) is 3.8% for the trace model, 4.3% for the modulo model, and 12.8% for the probabilistic model compared to FPGA execution. The results show that with the multi-level communication cost the accuracy is increased significantly, and accurate results can be achieved with arbitrary mappings.
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