Evaluating nanomagnetic logic circuit layouts using different clock schemes

Abstract

The complementary metal oxide semiconductor technology, CMOS, is reaching its physical limitations, as the transistors’ feature size decreases. A promising alternative is the nanomagnetic logic technology (NML), a paradigm of field-coupled nanocomputing. This technology applies single domain nanomagnets to implement digital logic with switching energies that are orders of magnitude lower than a CMOS transistor due to the complete absence of static energy dissipation. When designing nanomagnetic circuitry, several challenges arise, such as the design of a clocking system able to avoid signal disruption due to the thermal noise effect. In this paper, we compare four NML clocking schemes: BANCS, USE, RES, and 2DDWave by analyzing scalability and area overhead of combinational and sequential circuits.