Abstract
As the energy consumption has been surging in an unsustainable way, it is important to understand the impact of existing architecture designs from energy efficiency perspective, which is especially valuable for High Performance Computing (HPC) and datacenter environment hosting tens of thousands of servers. One obstacle hindering the advance of comprehensive evaluation on energy efficiency is the deficient power measuring approach. Most of the energy study relies on either external power meters or power models, both of these two methods contain intrinsic drawbacks in their practical adoption and measuring accuracy. Fortunately, the advent of Intel Running Average Power Limit (RAPL) interfaces has promoted the power measurement ability into next level, with higher accuracy and finer time resolution. Therefore, we argue it is the exact time to conduct an in-depth evaluation of the existing architecture designs to understand their impact on system energy efficiency. In this paper, we leverage representative benchmark suites including serial and parallel workloads from diverse domains to evaluate the architecture features such as Non Uniform Memory Access (NUMA), Simultaneous Multithreading (SMT) and Turbo Boost. The energy is tracked at subcomponent level such as Central Processing Unit (CPU) cores, uncore components and Dynamic Random-Access Memory (DRAM) through exploiting the power measurement ability exposed by RAPL. The experiments reveal non-intuitive results: 1) the mismatch between local compute and remote memory node caused by NUMA effect not only generates dramatic power and energy surge but also deteriorates the energy efficiency significantly; 2) for multithreaded application such as the Princeton Application Repository for Shared-Memory Computers (PARSEC), most of the workloads benefit a notable increase of energy efficiency using SMT, with more than 40% decline in average power consumption; 3) Turbo Boost is effective to accelerate the workload execution and further preserve the energy, however it may not be applicable on system with tight power budget.
Highlights
The advancements in computer architecture are undoubtedly pushing the frontier of system performance, fulfilling the prophecy of Moore’s Law
The power measurement ability exposed by Running Average Power Limit (RAPL) enables measuring the system energy consumption at fine granularity on multiple system components that was impossible before, which provides an unique opportunity to reason about how architecture designs affect the system energy consumption in unprecedented details
While PARSEC benchmark suite represents the emerging multi-core applications incorporating workloads from multiple domains, and NAS Parallel Benchmarks-Message Passing Interface (NPB-MPI) stands for the traditional HPC workloads derived from NASA real fluid computational applications
Summary
The advancements in computer architecture are undoubtedly pushing the frontier of system performance, fulfilling the prophecy of Moore’s Law. The ability of power measurement plays an important role in energy study, since measurement at fine granularity as well as with high accuracy can reveal more details about system behaviors on energy consumption. We argue the existing power measurement approaches are either impractical or inaccurate to evaluate the impact of different architecture designs on system energy consumption especially at subcomponent granularity. The power measurement ability exposed by RAPL enables measuring the system energy consumption at fine granularity (approximately 1 millisecond interval) on multiple system components that was impossible before, which provides an unique opportunity to reason about how architecture designs affect the system energy consumption in unprecedented details.
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