EUV and immersion lithography integration in 7nm FPGA production

Abstract

The 7nm node is the first generation where EUV lithography has been employed to replace a few multi-patterning immersion layers in high-volume manufacturing. The insertion of EUV lithography in the 7nm node can simplify the production process, reduce the cycle time, improve performance, and enhance yield. However, in order to fully take advantage of these benefits, we need to overcome new challenges introduced by EUV technology. In this paper, we present how to integrate 193nm immersion and EUV lithography in production and optimize the critical steps in the process. Our 7nm product was initially taped out with full 193nm-immersion masks. When the immersion process stabilized with a decent yield, we taped out n EUV layers to replace 3n immersion layers in the product. To migrate our production from the immersion process to the EUV process smoothly, we started a few Lots with splits of the immersion and the EUV processes. Some wafers went through the full immersion lithography process and the rest of the wafers went through the hybrid lithography process with about n layers using EUV. At the end, we compared the Si data of the two processes. After a few iterations of tweaking, the EUV process can provide better performance and higher yield than the immersion process. In this report, we also provide examples of how the better CD control with the EUV mask can be achieved, the Edge Placement Error (EPE) can be reduced and the uniformity of the EUV back-end-of-line (BEOL) layer can be improved during EUV process development.